A signal generation circuit includes: a clock signal generator configured to generate a clock signal and to change a frequency of the clock signal in response to a select signal; a transmission control circuit configured to control transmission of the clock signal based on the select signal; and a counter configured to perform an operation among a count operation and a count stop operation based on an output signal of the transmission control circuit and to output the select signal based on a result of performing the operation. When the counter performs the count operation in response to the clock signal output from the transmission control circuit, the counter outputs a most significant bit (MSB) among its count bits as the select signal.