Abstract:
A signal generation circuit includes: a clock signal generator configured to generate a clock signal and to change a frequency of the clock signal in response to a select signal; a transmission control circuit configured to control transmission of the clock signal based on the select signal; and a counter configured to perform an operation among a count operation and a count stop operation based on an output signal of the transmission control circuit and to output the select signal based on a result of performing the operation. When the counter performs the count operation in response to the clock signal output from the transmission control circuit, the counter outputs a most significant bit (MSB) among its count bits as the select signal.
Abstract:
A switching regulator may include; an inductor connected to a switch node, a power switch connected to the switch node and configured to apply a first voltage to the switch node in response to a first control signal and to apply a second voltage to the switch node in response to a second control signal, and a controller configured to generate the first control signal and the second control signal. The second control signal transitions from low to high following a first dead time after the first control signal transitions from low to high, the first control signal transitions from high to low following a second dead time after the second control signal transitions from high to low level, and an inductor current flowing through the inductor flows in a first direction during the first dead time and in a second direction, different from the first direction, during the second dead time.