发明授权
- 专利标题: Multi-chip packages with reduced power distribution network noise
- 专利标题(中): 具有降低配电网络噪声的多芯片封装
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申请号: US13646477申请日: 2012-10-05
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公开(公告)号: US09129935B1公开(公告)日: 2015-09-08
- 发明人: Karthik Chandrasekar , Arifur Rahman , Jeffrey Tyhach
- 申请人: Karthik Chandrasekar , Arifur Rahman , Jeffrey Tyhach
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Treyz Law Group
- 代理商 Jason Tsai
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L49/02 ; H01L21/50 ; H01L21/48 ; H01L23/498 ; H01L25/065
摘要:
A multi-chip package that includes multiple integrated circuits is provided. An integrated circuit in the multi-chip package may be mounted on an interposer. The interposer may be mounted on a package substrate. The integrated circuit may have internal power supply terminals coupled to on-package decoupling (OPD) capacitor circuitry that are formed as part of the package substrate. The power supply terminals on the integrated circuit may be coupled to conductive routing paths and through-silicon vias (TSVs) in the interposer via microbumps. The through-silicon vias in the interposer may be coupled to the OPD capacitor circuitry via flip-chip bumps. The conductive routing paths and the TSVs in the interposer may be coupled to the internal integrated circuit power supply terminals in a way that minimizes power supply resonance noise.
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