Invention Grant
- Patent Title: Process for fabricating a three-dimensional integrated structure with improved heat dissipation, and corresponding three-dimensional integrated structure
- Patent Title (中): 用于制造具有改善的散热的三维一体化结构的工艺，以及相应的三维一体化结构
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Application No.: US14293341Application Date: 2014-06-02
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Publication No.: US09136233B2Publication Date: 2015-09-15
- Inventor: Laurent-Luc Chapelon
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelctronis (Crolles 2) SAS
- Current Assignee: STMicroelctronis (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Gardere Wynne Sewell LLP
- Priority: FR1355215 20130606
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/30 ; H01L23/00 ; H01L23/427 ; H01L25/065 ; H01L25/00 ; H01L23/13 ; H01L23/31 ; H01L23/498
Abstract:
A three-dimensional integrated structure includes a first integrated circuit having a substrate assembled in an interlocking manner with a second integrated circuit having a substrate. The substrate of the first integrated circuit comprises first pores separated by first partitions, and the substrate of the second integrated circuit comprises second pores separated by second partitions. The first partitions interlock with the second pores and the second partitions interlock with the first pores so as to define at least one region bounded by the two substrates. A phase-change material is retained within the at least one region.
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