Invention Grant
- Patent Title: Semiconductor constructions
- Patent Title (中): 半导体结构
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Application No.: US13860427Application Date: 2013-04-10
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Publication No.: US09136331B2Publication Date: 2015-09-15
- Inventor: Chris Larsen , Alex J. Schrinsky , John D. Hopkins , Matthew King
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/76

Abstract:
Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X.
Public/Granted literature
- US20140306323A1 Semiconductor Constructions Public/Granted day:2014-10-16
Information query
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