Invention Grant
US09136356B2 Non-planar field effect transistor having a semiconductor fin and method for manufacturing
有权
具有半导体鳍片的非平面场效应晶体管及其制造方法
- Patent Title: Non-planar field effect transistor having a semiconductor fin and method for manufacturing
- Patent Title (中): 具有半导体鳍片的非平面场效应晶体管及其制造方法
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Application No.: US14176873Application Date: 2014-02-10
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Publication No.: US09136356B2Publication Date: 2015-09-15
- Inventor: Chien-Chih Lin , Long-Jie Hong , Chih-Lin Wang , Chia-Der Chang
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Maschoff Brennan
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L21/311

Abstract:
A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.
Public/Granted literature
- US20150228763A1 NON-PLANAR FIELD EFFECT TRANSISTOR HAVING A SEMICONDUCTOR FIN AND METHOD FOR MANUFACTURING Public/Granted day:2015-08-13
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