Invention Grant
US09136384B2 Method for the formation of a FinFET device having partially dielectric isolated Fin structure
有权
用于形成具有部分电介质隔离的Fin结构的FinFET器件的方法
- Patent Title: Method for the formation of a FinFET device having partially dielectric isolated Fin structure
- Patent Title (中): 用于形成具有部分电介质隔离的Fin结构的FinFET器件的方法
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Application No.: US14097570Application Date: 2013-12-05
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Publication No.: US09136384B2Publication Date: 2015-09-15
- Inventor: Nicolas Loubet , Ronald Kevin Sampson
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/78 ; H01L29/66 ; H01L29/06

Abstract:
A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.
Public/Granted literature
- US20150162434A1 METHOD FOR THE FORMATION OF A FINFET DEVICE HAVING PARTIALLY DIELECTRIC ISOLATED FIN STRUCTURE Public/Granted day:2015-06-11
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