公开(公告)号：US09601381B2

公开(公告)日：2017-03-21

申请号：US14097565

申请日：2013-12-05

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

公开(公告)号：US09136384B2

公开(公告)日：2015-09-15

申请号：US14097570

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Ronald Kevin Sampson

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.

Abstract translation: 将半导体材料图案化以限定与底层基板绝缘的细长翅片。 多晶硅半导体材料沉积在细长翅片之上并在细长翅片之间，并且被图案化以限定延伸到在晶体管沟槽处垂直交叉在细长翅片上的细长门。 侧壁间隔件形成在细长门的侧壁上。 位于细长门之间的细长翅片的部分与下面的绝缘体一起被去除以暴露下面的基底。 然后在细长门之间的位置从下面的衬底外延生长一个或多个半导体材料层。 一个或多个半导体材料层可以包括未掺杂的外延层和上覆的掺杂外延层。 外延材料限定晶体管的源极或漏极。

公开(公告)号：US20150162433A1

公开(公告)日：2015-06-11

申请号：US14097565

申请日：2013-12-05

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract translation: 第一半导体材料的细长散热片与下层基底层（SOI或本体型）绝缘和形成。 然后形成第二半导体材料的细长的栅极，以在沟道区域上跨过细长的翅片，并且栅极侧壁被侧壁间隔物覆盖。 提供保护材料以覆盖下面的基底层并且在细长门之间限定细长翅片的侧壁上的侧壁间隔物。 位于保护材料侧壁间隔件（但不在细长门下）的细长翅片的第一半导体材料和绝缘材料被去除以形成与沟道区域对准的沟槽。 然后在细长门之间的每个沟槽内外延生长另外的半导体材料，以形成邻近由位于细长栅极下方的第一半导体材料的细长鳍片形成的沟道区域的源极 - 漏极区域。

公开(公告)号：US20150162434A1

公开(公告)日：2015-06-11

申请号：US14097570

申请日：2013-12-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Ronald Kevin Sampson

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel. Sidewall spacers are formed on side walls of the elongated gates. Portions of the elongated fins located between the elongated gates are removed, along with the underlying insulation, to expose the underlying substrate. One or more semiconductor material layers are then epitaxially grown from the underlying substrate at locations between the elongated gates. The one or more semiconductor material layers may include an undoped epi-layer and an overlying doped epi-layer. The epitaxial material defines a source or drain of the transistor.