发明授权
US09141831B2 Scheduler, security context cache, packet processor, and authentication, encryption modules
有权
调度器，安全上下文缓存，数据包处理器和认证，加密模块
- 专利标题： Scheduler, security context cache, packet processor, and authentication, encryption modules
- 专利标题（中）： 调度器，安全上下文缓存，数据包处理器和认证，加密模块
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申请号： US13165190申请日： 2011-06-21
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公开(公告)号： US09141831B2公开(公告)日： 2015-09-22
- 发明人: Amritpal Singh Mundra , Denis Roland Beaudoin
- 申请人： Amritpal Singh Mundra , Denis Roland Beaudoin
- 申请人地址： US TX Dallas
- 专利权人： TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人： TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人地址： US TX Dallas
- 代理商 Lawrence J. Bassuk; Frank D. Cimino
- 主分类号： G06F21/72
- IPC分类号： G06F21/72 ; H04L9/06 ; H04L29/06
摘要：
An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
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