A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure and a second clock origin, where the second clock origin is connected to the first clock distribution structure with a plurality of through layer vias, and where the second layer thickness is less than 1 micrometer.