Invention Grant
- Patent Title: Multi-tiered semiconductor devices and associated methods
- Patent Title (中): 多层半导体器件及相关方法
-
Application No.: US14274933Application Date: 2014-05-12
-
Publication No.: US09147691B2Publication Date: 2015-09-29
- Inventor: Nishant Sinha
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/311 ; H01L27/06 ; H01L29/788 ; H01L29/786
Abstract:
Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.
Public/Granted literature
- US20140246716A1 MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS Public/Granted day:2014-09-04
Information query
IPC分类:
