An IGBT is disclosed with a high emitter-gate capacitance, wherein an active cell region can include plural emitter and gate regions. A termination edge region can include a varied lateral doping region VLD. Each gate polysilicon layer can be arranged at a surface of the semiconductor substrate in the gate regions, separated from the semiconductor substrate by a first insulating layer. A first SIPOS layer and a covering second insulating layer overlie at least portions of the gate polysilicon layer. In a central area, the gate polysilicon layer is in electrical contact with the overlying first SIPOS layer whereas, in a peripheral area, the gate polysilicon layer is electrically separated from the overlying first SIPOS layer. A substrate surface at the VLD region is in electrical contact with a second SIPOS layer, and an increased gate-emitter capacitance may be achieved by slightly modifying etch masks during manufacturing.