Invention Grant
- Patent Title: Logical address translation
- Patent Title (中): 逻辑地址转换
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Application No.: US14255525Application Date: 2014-04-17
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Publication No.: US09164701B2Publication Date: 2015-10-20
- Inventor: Martin L. Culley , Troy A. Manning , Troy D. Larsen
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06 ; G06F12/02 ; G06F12/14 ; G06F12/04 ; G06F12/10

Abstract:
The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
Public/Granted literature
- US20140317374A1 LOGICAL ADDRESS TRANSLATION Public/Granted day:2014-10-23
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