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    SENSE AMPLIFIERS AS STATIC RANDOM ACCESS MEMORY CACHE
    1.
    发明公开
    SENSE AMPLIFIERS AS STATIC RANDOM ACCESS MEMORY CACHE 审中-公开

    公开(公告)号：US20240256448A1

    公开(公告)日：2024-08-01

    申请号：US18414640

    申请日：2024-01-17

    Applicant: Micron Technology, Inc.

    Inventor： Peter L. Brown ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/1032 ,  G06F2212/221

    Abstract: Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.

    VECTOR REGISTERS IMPLEMENTED IN MEMORY
    3.
    发明申请
    VECTOR REGISTERS IMPLEMENTED IN MEMORY 有权

    公开(公告)号：US20220066777A1

    公开(公告)日：2022-03-03

    申请号：US17454171

    申请日：2021-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F9/30 ,  G06F12/02

    Abstract: Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.

    CODEWORDS THAT SPAN PAGES OF MEMORY
    7.
    发明申请
    CODEWORDS THAT SPAN PAGES OF MEMORY 有权
    编写存储空间页码

    公开(公告)号：US20150324252A1

    公开(公告)日：2015-11-12

    申请号：US14802005

    申请日：2015-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Troy D. Larsen ,  Martin L. Culley

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906

    Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.

    Abstract translation: 本公开包括跨越存储器页面的码字的装置和方法。 许多方法包括将主码字的第一部分写入第一存储器块中的第一页，并将主码字的第二部分写入第二存储器块中的第二页。 主码字可以被包括在次码字中。 该方法可以包括将次码字的第一部分写入存储器中，并将次码字的第二部分写入与辅助码字的第一部分不同的存储器页和块。

    COHERENT MEMORY ACCESS
    8.
    发明公开
    COHERENT MEMORY ACCESS 审中-公开

    公开(公告)号：US20240296124A1

    公开(公告)日：2024-09-05

    申请号：US18129559

    申请日：2023-03-31

    Applicant: Micron Technology, Inc.

    Inventor： Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F12/0877

    CPC classification number: G06F12/0877 ,  G06F2212/221 ,  G06F2212/656

    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

    COHERENT MEMORY ACCESS
    10.
    发明申请
    COHERENT MEMORY ACCESS 有权

    公开(公告)号：US20220318148A1

    公开(公告)日：2022-10-06

    申请号：US17843387

    申请日：2022-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F12/0877

    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

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