Invention Grant
US09171754B2 Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process 有权
包括对半导体结构中的层间电介质的一部分进行蚀刻的方法,脱气工艺和预清洗工艺

Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
Abstract:
A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.
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