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    METHOD FOR DETECTING DEFECTS IN A DIFFUSION BARRIER LAYER
    1.
    发明申请
    METHOD FOR DETECTING DEFECTS IN A DIFFUSION BARRIER LAYER 有权
    用于检测扩张障碍层中的缺陷的方法

    公开(公告)号：US20150111316A1

    公开(公告)日：2015-04-23

    申请号：US14060147

    申请日：2013-10-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Frank Koschinsky ,  Bernd Hintze ,  Dirk Utess

    IPC: H01L21/66 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L22/12 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76868 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.

    Abstract translation: 一种提供包括扩散阻挡层和籽晶层的半导体结构的方法，种子层包括铜和不同于铜的金属的合金，在种子层上沉积导电材料，进行退火处理，其中至少 除了铜之外的金属的第一部分通过导电材料扩散到扩散阻挡层的附近，并且其中在扩散阻挡层中存在缺陷的情况下，除铜之外的金属的第二部分指示 缺陷保留在缺陷附近，测量半导体结构的至少一部分中除铜以外的金属的分布，并且从测定的除了铜以外的金属的分布确定金属的第二部分 除了铜以外。

    METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR STRUCTURE, A DEGAS PROCESS AND A PRECLEAN PROCESS
    2.
    发明申请
    METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR STRUCTURE, A DEGAS PROCESS AND A PRECLEAN PROCESS 有权
    包括在半导体结构中的层间介质的蚀刻的方法，A DEGAS过程和PRECLEAN过程

    公开(公告)号：US20140349478A1

    公开(公告)日：2014-11-27

    申请号：US13901739

    申请日：2013-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Frank Koschinsky ,  Bernd Hintze ,  Oliver Witnik

    IPC: H01L21/768

    CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76826 ,  H01L21/76828

    Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.

    Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括具有前侧和背面的基板，包括设置在基板的前侧的铜的导电特征以及设置在导电特征上的低k层间电介质。 蚀刻层间电介质的一部分。 在蚀刻工艺中，导电特征的表面被暴露。 进行脱气处理，其中半导体结构暴露于第一气体，并且其中半导体结构从背侧和从前侧被加热。 可以进行预清洗处理。 预清洗方法可以包括第一阶段，其中半导体结构暴露于基本上非电离的第二气体和第二相，其中半导体结构暴露于由第二气体产生的等离子体。

    Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process
    4.
    发明授权
    Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process 有权
    包括对半导体结构中的层间电介质的一部分进行蚀刻的方法，脱气工艺和预清洗工艺

    公开(公告)号：US09171754B2

    公开(公告)日：2015-10-27

    申请号：US13901739

    申请日：2013-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Frank Koschinsky ,  Bernd Hintze ,  Oliver Witnik

    IPC: H01L21/00 ,  H01L21/768

    CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76826 ,  H01L21/76828

    Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.

    Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括具有前侧和背面的基板，包括设置在基板的前侧的铜的导电特征以及设置在导电特征上的低k层间电介质。 蚀刻层间电介质的一部分。 在蚀刻工艺中，导电特征的表面被暴露。 进行脱气处理，其中半导体结构暴露于第一气体，并且其中半导体结构从背侧和从前侧被加热。 可以进行预清洗处理。 预清洗方法可以包括第一阶段，其中半导体结构暴露于基本上非电离的第二气体和第二相，其中半导体结构暴露于由第二气体产生的等离子体。

    METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION
    5.
    发明申请
    METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION 审中-公开
    包括从半导体结构中去除硬质合金的方法和用碱性溶液冲洗半导体结构

    公开(公告)号：US20140349479A1

    公开(公告)日：2014-11-27

    申请号：US13901778

    申请日：2013-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Oliver Mieth ,  Torsten Huisinga ,  Carsten Peters ,  Bernd Hintze ,  Grit Bonsdorf

    IPC: H01L21/768

    CPC classification number: H01L21/76897 ,  C23F1/32 ,  C23F1/38 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814

    Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes an electrically conductive feature including a first metal, a dielectric material provided over the electrically conductive feature and a hardmask. The hardmask includes a hardmask material and is provided over the dielectric material. An opening is provided in the interlayer dielectric and the hardmask. A portion of the electrically conductive feature is exposed at a bottom of the opening. The hardmask is removed. The removal of the hardmask includes exposing the semiconductor structure to an etching solution including hydrogen peroxide and a corrosion inhibitor. After the removal of the hardmask, the semiconductor structure is rinsed. Rinsing the semiconductor structure includes exposing the semiconductor structure to an alkaline rinse solution.

    Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括导电特征，其包括第一金属，设置在导电特征上的介电材料和硬掩模。 硬掩模包括硬掩模材料并且设置在电介质材料上。 在层间电介质和硬掩模中设置开口。 导电特征的一部分暴露在开口的底部。 硬掩模被删除。 去除硬掩模包括将半导体结构暴露于包括过氧化氢和腐蚀抑制剂的蚀刻溶液。 在去除硬掩模之后，冲洗半导体结构。 冲洗半导体结构包括将半导体结构暴露于碱性冲洗溶液中。

    Method for detecting defects in a diffusion barrier layer
    8.
    发明授权
    Method for detecting defects in a diffusion barrier layer 有权
    用于检测扩散阻挡层中的缺陷的方法

    公开(公告)号：US09147618B2

    公开(公告)日：2015-09-29

    申请号：US14060147

    申请日：2013-10-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Frank Koschinsky ,  Bernd Hintze ,  Dirk Utess

    IPC: H01L21/66 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L22/12 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76868 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.

    Abstract translation: 一种提供包括扩散阻挡层和籽晶层的半导体结构的方法，种子层包括铜和不同于铜的金属的合金，在种子层上沉积导电材料，进行退火处理，其中至少 除了铜以外的金属的第一部分通过导电材料扩散到扩散阻挡层的附近，并且其中，在扩散阻挡层中存在缺陷的情况下，除铜之外的金属的第二部分指示 缺陷保留在缺陷附近，测量半导体结构的至少一部分中除铜以外的金属的分布，并且从测定的除了铜以外的金属的分布确定金属的第二部分 除了铜以外。

    METHODS OF FORMING BARRIER LAYERS FOR CONDUCTIVE COPPER STRUCTURES
    10.
    发明申请
    METHODS OF FORMING BARRIER LAYERS FOR CONDUCTIVE COPPER STRUCTURES 审中-公开
    导电铜结构形成障碍层的方法

    公开(公告)号：US20140273436A1

    公开(公告)日：2014-09-18

    申请号：US13834292

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Bernd Hintze ,  Frank Koschinsky

    IPC: H01L21/768

    CPC classification number: H01L21/76856 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76859 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in at least the trench/via, after forming said barrier layer, performing at least one process operation to introduce manganese into the barrier layer and thereby define a manganese-containing barrier layer, forming a substantially pure copper-based seed layer above the manganese-containing barrier layer, depositing a bulk copper-based material above the copper-based seed layer so as to overfill the trench/via, and removing excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure.

    Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在形成所述阻挡层之后在至少沟槽/通孔中形成阻挡层，进行至少一种将锰引入阻挡层中的工艺操作，以及 从而限定含锰阻挡层，在含锰阻挡层上形成基本上纯的铜基种子层，在铜基种子层上沉积大块铜基材料，以覆盖沟槽/通孔，以及 去除位于沟槽/通孔外部的多余材料，从而限定铜基导电结构。

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