Invention Grant
- Patent Title: Methods for fabricating integrated circuits using self-aligned quadruple patterning
- Patent Title (中): 使用自对准四重图案化制造集成电路的方法
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Application No.: US14106347Application Date: 2013-12-13
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Publication No.: US09171764B2Publication Date: 2015-10-27
- Inventor: Ryan Ryoung Han Kim , Jason Cantone
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/8238 ; H01L27/11 ; H01L21/306 ; H01L21/308

Abstract:
Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes etching an upper mandrel layer to form upper mandrels. At least one upper mandrel has a first critical dimension and at least one upper mandrel has a second critical dimension not equal to the first critical dimension. The method further includes forming upper spacers adjacent the upper mandrels and etching a lower mandrel layer using the upper spacers as an etch mask to form lower mandrels. The method also includes forming lower spacers adjacent the lower mandrels and etching a material using the lower spacers as an etch mask to form variably spaced structures.
Public/Granted literature
- US20150170973A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING Public/Granted day:2015-06-18
Information query
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