Invention Grant
- Patent Title: Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device
- Patent Title (中): 半导体布局图案的制造方法，半导体装置的制造方法以及半导体装置
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Application No.: US13674965Application Date: 2012-11-13
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Publication No.: US09171898B2Publication Date: 2015-10-27
- Inventor: Yu-Shiang Yang , Cheng-Te Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/36 ; H01L29/02 ; H01L21/308 ; H01L21/762
Abstract:
A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns.
Public/Granted literature
Information query
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