Invention Grant
US09172339B2 Cascode bias of power MOS transistors 有权
功率MOS晶体管的串联偏置

Cascode bias of power MOS transistors
Abstract:
There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry adapted for dynamically generating a dynamic bias control signal so as to cause the cascode MOS transistor of the switch to be ‘Off’ in the low power mode.
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