Invention Grant
- Patent Title: Cascode bias of power MOS transistors
- Patent Title (中): 功率MOS晶体管的串联偏置
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Application No.: US14136469Application Date: 2013-12-20
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Publication No.: US09172339B2Publication Date: 2015-10-27
- Inventor: Vincent Binet , Emmanuel Allier , Francois Amiard
- Applicant: ST-Ericsson SA
- Applicant Address: CH Plan-les-Ouates
- Assignee: ST-ERICSSON SA
- Current Assignee: ST-ERICSSON SA
- Current Assignee Address: CH Plan-les-Ouates
- Agency: Patent Portfolio Builders PLLC
- Priority: EP12306692 20121227
- Main IPC: H03F3/217
- IPC: H03F3/217 ; H03F1/02 ; H03F3/72

Abstract:
There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry adapted for dynamically generating a dynamic bias control signal so as to cause the cascode MOS transistor of the switch to be ‘Off’ in the low power mode.
Public/Granted literature
- US20140184328A1 CASCODE BIAS OF POWER MOS TRANSISTORS Public/Granted day:2014-07-03
Information query
IPC分类: