Invention Grant
US09183338B1 Single-event upset mitigation in circuit design for programmable integrated circuits
有权
用于可编程集成电路的电路设计中的单事件缓解
- Patent Title: Single-event upset mitigation in circuit design for programmable integrated circuits
- Patent Title (中): 用于可编程集成电路的电路设计中的单事件缓解
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Application No.: US14487286Application Date: 2014-09-16
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Publication No.: US09183338B1Publication Date: 2015-11-10
- Inventor: Praful Jain , Pierre Maillard
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Robert Brush
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
In an example, a method of implementing a circuit design for a programmable integrated circuit (IC) begins by identifying combinatorial logic functions of the circuit design. The method maps, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of LUTs being more susceptible to single event upsets than the first type of LUTs. The method generates a first physical implementation of the circuit design for the programmable IC based on the mapping.
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