Invention Grant
- Patent Title: Circuits and methods of a self-timed high speed SRAM
- Patent Title (中): 自定时高速SRAM的电路和方法
-
Application No.: US14042392Application Date: 2013-09-30
-
Publication No.: US09183897B2Publication Date: 2015-11-10
- Inventor: Shine C. Chung
- Applicant: Shine C. Chung
- Main IPC: G11C7/06
- IPC: G11C7/06 ; G11C7/22 ; G11C11/419 ; G11C11/418

Abstract:
Circuits and methods for precisely self-timed SRAM memory are disclosed to track the wordline and/or bitline/bitline bar (BL/BLB) propagation delays. At least one reference cell can be placed near the far end of a driver to drive a selected wordline or a reference wordline. When a wordline and/or a reference wordline is turned on, the reference cell can be selected not earlier than any selected SRAM cells and can activate a reference bitline (RBL) not later than any selected SRAM cells activating the BL or BLB. The activation of the RBL can be used to trigger at least one sense amplifier. The RBL can also be used to de-select wordline or reference wordline after the sense amplifier operation is complete to save power.
Public/Granted literature
- US20140092674A1 Circuits and Methods of a Self-Timed High Speed SRAM Public/Granted day:2014-04-03
Information query