Invention Grant
US09188642B2 Reconfigurable memory interface circuit to support a built-in memory scan chain
有权
可重构存储器接口电路，支持内置的内存扫描链
- Patent Title: Reconfigurable memory interface circuit to support a built-in memory scan chain
- Patent Title (中): 可重构存储器接口电路，支持内置的内存扫描链
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Application No.: US13975277Application Date: 2013-08-23
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Publication No.: US09188642B2Publication Date: 2015-11-17
- Inventor: Chirag Gulati , Ritu Chaba , Lakshmikantha Holla Vakwadi
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox LLP
- Main IPC: G01R31/3185
- IPC: G01R31/3185 ; G11C29/32 ; G11C29/36
Abstract:
A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.
Public/Granted literature
- US20150058686A1 RECONFIGURABLE MEMORY INTERFACE CIRCUIT TO SUPPORT A BUILT-IN MEMORY SCAN CHAIN Public/Granted day:2015-02-26
Information query
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