公开(公告)号：US09030863B2

公开(公告)日：2015-05-12

申请号：US14038434

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Rakesh Kumar Sinha ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C8/14 ,  H01L27/1104 ,  H01L27/1116

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract translation: 集成电路包括一个或多个位单元，耦合到所述一个或多个位单元的字线以及与所述字线布置以在其间具有电容的虚拟字线。 该电容提供了字线的升压或降压以辅助读和写操作。

公开(公告)号：US09064556B2

公开(公告)日：2015-06-23

申请号：US14061528

申请日：2013-10-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Lakshmikantha Holla Vakwadi ,  Sei Seung Yoon

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1075 ,  G11C11/419

Abstract: A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.

Abstract translation: 公开了一种伪双端口（PDP）存储器，其具有写入驱动器，该写入驱动器响应于要写入访问的位单元的位值而选择性地仅对位线对中的一个位线进行充电，同时放电剩余的一个 的位线和补码位线。 以这种方式，有利地减少了在读/写时钟周期期间读操作和写操作之间的清理时间。

公开(公告)号：US20150109865A1

公开(公告)日：2015-04-23

申请号：US14061528

申请日：2013-10-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Lakshmikantha Holla Vakwadi ,  Sei-Seung Yoon

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1075 ,  G11C11/419

Abstract: A pseudo dual port (PDP) memory is disclosed having a write driver that selectively precharges only one of a bit line and a complement bit line in a bit line pair responsive to a bit value to be written into an accessed bitcell while discharging a remaining one of the bit line and the complement bit line. In this fashion, the cleanup time between a read operation and a write operation during a read/write clock cycle is advantageously reduced.

Abstract translation: 公开了一种伪双端口（PDP）存储器，其具有写入驱动器，该写入驱动器响应于要写入访问的位单元的位值而选择性地仅对位线对中的一个位线进行充电，同时放电剩余的一个 的位线和补码位线。 以这种方式，有利地减少了在读/写时钟周期期间读操作和写操作之间的清理时间。

公开(公告)号：US08929153B1

公开(公告)日：2015-01-06

申请号：US13975254

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Rakesh Kumar Sinha ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.

Abstract translation: 公开了具有多重读取字线设计的存储器的各种装置和方法。 存储器可以包括排列成行的多个比特单元，连接到多个比特单元的第一子集的第一读取字线和连接到多个比特单元的第二子集的第二读取字线，其中 第一和第二子集位于同一行位单元格中。 一种方法可以包括在第一读取操作期间断言连接到排列在位单元行中的多个位单元的第一子集的第一读取字线，并且在第二读取操作期间断言第二读取字线 连接到所述多个位单元的第二子集，其中所述第一和第二子集位于同一行比特单元中。

公开(公告)号：US09188642B2

公开(公告)日：2015-11-17

申请号：US13975277

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Ritu Chaba ,  Lakshmikantha Holla Vakwadi

IPC: G01R31/3185 ,  G11C29/32 ,  G11C29/36

CPC classification number: G01R31/318541 ,  G01R31/318597 ,  G11C29/32 ,  G11C29/36 ,  G11C2029/3202 ,  G11C2029/3602

Abstract: A method of operating an apparatus in a functional mode and an ATPG scan mode and an apparatus for use in a functional mode and an ATPG scan mode are provided. The apparatus includes a set of latches including a first latch and a second latch. The first latch is operated as a master latch and the second latch is operated as a master latch in the functional mode. The first latch is operated as a master latch of a flip-flop and the second latch is operated as a slave latch of the flip-flop in the ATPG scan mode. In one configuration, the apparatus includes a plurality of latches including at least the first and second latches, an output of each of the latches is coupled to a digital circuit, the apparatus includes a plurality of functional inputs, and each of the functional inputs is input to the digital circuit.

Abstract translation: 提供了在功能模式和ATPG扫描模式下操作装置的方法以及用于功能模式和ATPG扫描模式的装置。 该装置包括一组锁存器，其包括第一锁存器和第二锁存器。 第一个锁存器作为主锁存器操作，第二个锁存器在功能模式下作为主锁存器运行。 第一个锁存器作为触发器的主锁存器操作，第二个锁存器在ATPG扫描模式下作为触发器的从锁存器操作。 在一种配置中，该装置包括至少包括第一和第二锁存器的多个锁存器，每个锁存器的输出耦合到数字电路，该装置包括多个功能输入，并且每个功能输入是 输入到数字电路。

公开(公告)号：US09111589B2

公开(公告)日：2015-08-18

申请号：US14018404

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Kumar Sinha ,  Chirag Gulati ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/22

CPC classification number: G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/227

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

Abstract translation: 公开了具有多字线设计的存储器的各种装置和方法。 存储器定时电路可以包括包括第一部分和第二部分的虚拟字线，并且还包括集中在伪字线的第二部分中的电容负载，连接到虚拟字线的第一部分的第一晶体管和 被配置为对所述虚拟字线充电;以及第二晶体管，连接到所述虚拟字线的第二部分，并且被配置为对所述虚拟字线进行放电。 一种方法可以包括使用第一晶体管对虚拟字线进行充电，以及使用第二晶体管对该虚拟字线进行放电，其中，所述虚拟字线包括第一部分和第二部分，并且还包括集中在所述第二部分中的电容负载 的虚拟字线。

公开(公告)号：US09165641B2

公开(公告)日：2015-10-20

申请号：US14106575

申请日：2013-12-13

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Ashish Akhilesh ,  Venkatasubramanian Narayanan

IPC: G11C11/00 ,  G11C11/417 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C7/12

Abstract: A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.

Abstract translation: 公开了一种存储器件偏置电路，该电路具有一对半导体器件，其被耦合以接收电源电压，该电源电压具有适于在有源模式下操作存储器件的电源电压电平，并可操作以向存储器件提供可调节的偏置电压， 大于在数据保持模式下操作存储器件的最小电压电平。 所述一对半导体器件包括第一半导体器件; 以及包括与第一半导体器件相反的半导体器件的第二半导体器件，使得该对半导体器件包括N型半导体器件和P型半导体器件中的每一个。 存储器件偏置电路还包括耦合到第二半导体器件并被配置为基于电源电压来调整第二半导体器件的操作的偏置调整电路。

公开(公告)号：US20150170736A1

公开(公告)日：2015-06-18

申请号：US14106575

申请日：2013-12-13

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Ashish Akhilesh ,  Venkatasubramanian Narayanan

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C7/12

Abstract: A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.

Abstract translation: 公开了一种存储器件偏置电路，该电路具有一对半导体器件，其被耦合以接收电源电压，该电源电压具有适于在有源模式下操作存储器件的电源电压电平，并可操作以向存储器件提供可调节的偏置电压， 大于在数据保持模式下操作存储器件的最小电压电平。 所述一对半导体器件包括第一半导体器件; 以及包括与第一半导体器件相反的半导体器件的第二半导体器件，使得该对半导体器件包括N型半导体器件和P型半导体器件中的每一个。 存储器件偏置电路还包括耦合到第二半导体器件并被配置为基于电源电压来调整第二半导体器件的操作的偏置调整电路。