发明授权
US09190532B2 Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby
有权
制造具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元以及由此形成的存储单元的方法
- 专利标题： Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby
- 专利标题（中）： 制造具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元以及由此形成的存储单元的方法
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申请号： US14240440申请日： 2012-08-08
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公开(公告)号： US09190532B2公开(公告)日： 2015-11-17
- 发明人: Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
- 申请人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
- 申请人地址： US CA San Jose
- 专利权人： Silicon Storage Technology, Inc.
- 当前专利权人： Silicon Storage Technology, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： DLA Piper LLP (US)
- 优先权： CN201110247064 20110824
- 国际申请： PCT/US2012/050022 WO 20120808
- 国际公布： WO2013/028358 WO 20130228
- 主分类号： H01L29/788
- IPC分类号： H01L29/788 ; H01L21/28 ; H01L29/423 ; H01L29/66 ; H01L27/115
摘要：
A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.