Invention Grant
- Patent Title: Cache coherency and processor consistency
- Patent Title (中): 缓存一致性和处理器一致性
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Application No.: US13729629Application Date: 2012-12-28
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Publication No.: US09195465B2Publication Date: 2015-11-24
- Inventor: Varun K. Mohandru , Fernando Latorre , Li-Gao Zei , Allan D. Knies , Rami May , Lutz Naethke
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F12/08

Abstract:
Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.
Public/Granted literature
- US20140189253A1 CACHE COHERENCY AND PROCESSOR CONSISTENCY Public/Granted day:2014-07-03
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