In a memory cell including first to third transistors, the potential of a bit line is set to VDD or GND when data is written through the first transistor. In a standby period, the potential of the bit line is set to GND. In reading operation, the bit line is brought into a floating state at GND, and a source line is set to a potential VDD−α, consequently, the third transistor is turned on. Then, the potential of the source line is output according to the potential of a gate of the second transistor. Note that α is set so that the second transistor is surely off even when the potential of the gate of the second transistor becomes lower from VDD by ΔV in the standby period. That is, Vth+ΔV