Invention Grant
- Patent Title: Self-aligned gated emitter tip arrays
- Patent Title (中): 自对准栅极发射极尖阵列
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Application No.: US14067668Application Date: 2013-10-30
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Publication No.: US09196447B2Publication Date: 2015-11-24
- Inventor: Arash Akhavan Fomani , Luis Fernando Velasquez-Garcia , Akintunde Ibitayo Akinwande
- Applicant: Massachusetts Institutes of Technology
- Applicant Address: US MA Cambridge
- Assignee: Massachusetts Institutes of Technology
- Current Assignee: Massachusetts Institutes of Technology
- Current Assignee Address: US MA Cambridge
- Agency: McCarter & English, LLP
- Main IPC: H01J9/02
- IPC: H01J9/02 ; H01J1/304 ; H01L21/00

Abstract:
Methods for fabrication of self-aligned gated tip arrays are described. The methods are performed on a multilayer structure that includes a substrate, an intermediate layer that includes a dielectric material disposed over at least a portion of the substrate, and at least one gate electrode layer disposed over at least a portion of the intermediate layer. The method includes forming a via through at least a portion of the at least one gate electrode layer. The via through the at least one gate electrode layer defines a gate aperture. The method also includes etching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure.
Public/Granted literature
- US20140285084A1 SELF-ALIGNED GATED EMITTER TIP ARRAYS Public/Granted day:2014-09-25
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