公开(公告)号：US09196447B2

公开(公告)日：2015-11-24

申请号：US14067668

申请日：2013-10-30

Applicant: Massachusetts Institutes of Technology

Inventor： Arash Akhavan Fomani ,  Luis Fernando Velasquez-Garcia ,  Akintunde Ibitayo Akinwande

IPC: H01J9/02 ,  H01J1/304 ,  H01L21/00

CPC classification number: H01J9/025 ,  H01J1/304 ,  H01J2201/30411 ,  H01L21/00 ,  H01T19/04 ,  H01T23/00

Abstract: Methods for fabrication of self-aligned gated tip arrays are described. The methods are performed on a multilayer structure that includes a substrate, an intermediate layer that includes a dielectric material disposed over at least a portion of the substrate, and at least one gate electrode layer disposed over at least a portion of the intermediate layer. The method includes forming a via through at least a portion of the at least one gate electrode layer. The via through the at least one gate electrode layer defines a gate aperture. The method also includes etching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure.

Abstract translation: 描述了自对准浇口尖端阵列的制造方法。 该方法在包括衬底，包括设置在衬底的至少一部分上的电介质材料的中间层以及设置在中间层的至少一部分上的至少一个栅电极层的多层结构上进行。 该方法包括通过至少一个栅极电极层的至少一部分形成通孔。 通过至少一个栅极电极层的通孔限定栅极孔径。 该方法还包括蚀刻靠近栅极孔的中间层的至少一部分，使得在多层结构中形成至少部分被沟槽包围的发射极结构。