Invention Grant
US09202918B2 Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices
有权
在FinFET半导体器件上形成应力层的方法和所得到的器件
- Patent Title: Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices
- Patent Title (中): 在FinFET半导体器件上形成应力层的方法和所得到的器件
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Application No.: US14030540Application Date: 2013-09-18
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Publication No.: US09202918B2Publication Date: 2015-12-01
- Inventor: Ruilong Xie , Ryan Ryoung-han Kim , William J. Taylor, Jr.
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/78 ; H01L29/66
Abstract:
One method includes forming a raised isolation structure with a recess above a substrate, forming a gate structure above the fin, forming a plurality of spaced-apart buried fin contact structures within the recess and forming a stress-inducing material layer above the buried fin contact structures. One device includes a plurality of spaced-apart buried fin contact structures positioned within a recess in a raised isolation structure on opposite sides of a gate structure, a stress-inducing material layer formed above the buried fin contact structures and a source/drain contact that extends through the stress-inducing material layer.
Public/Granted literature
- US20150076609A1 METHODS OF FORMING STRESSED LAYERS ON FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES Public/Granted day:2015-03-19
Information query
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