公开(公告)号：US10957544B2

公开(公告)日：2021-03-23

申请号：US15484173

申请日：2017-04-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Andrew M. Greene ,  Ryan O. Jung ,  Ruilong Xie

IPC分类号： H01L21/283 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L27/02 ,  H01L21/033 ,  H01L21/3105

摘要： A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.

公开(公告)号：US10832944B2

公开(公告)日：2020-11-10

申请号：US16177854

申请日：2018-11-01

申请人： GLOBALFOUNDRIES INC.

发明人： Nicholas V. LiCausi ,  Chanro Park ,  Ruilong Xie ,  Andre P. Labonte

IPC分类号： H01L21/768

摘要： An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

公开(公告)号：US10797154B2

公开(公告)日：2020-10-06

申请号：US15190778

申请日：2016-06-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

发明人： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC分类号： H01L21/768 ,  H01L29/66 ,  H01L21/283 ,  H01L27/088 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/08

摘要： A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US20200312764A1

公开(公告)日：2020-10-01

申请号：US16363585

申请日：2019-03-25

申请人： GLOBALFOUNDRIES Inc.

发明人： Guoxiang Ning ,  Ruilong Xie ,  Lei Sun

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

摘要： Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

公开(公告)号：US10790363B2

公开(公告)日：2020-09-29

申请号：US16054033

申请日：2018-08-03

申请人： GLOBALFOUNDRIES INC.

发明人： Laertis Economikos ,  Kevin J. Ryan ,  Ruilong Xie ,  Hui Zang

IPC分类号： H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/66

摘要： The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

公开(公告)号：US10777465B2

公开(公告)日：2020-09-15

申请号：US15868199

申请日：2018-01-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Chun-chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/51

摘要： Structures including a vertical-transport field-effect transistor and a planar field-effect transistor, and methods of forming such structures. First and second sacrificial fins are respectively formed over first and second areas of the first device region. One or more semiconductor fins of the vertical-transport field-effect transistor are formed over the second device region. A first gate electrode of the planar field-effect transistor, which is arranged on the first device region between the first sacrificial fin and the second sacrificial fin, and a second gate electrode of the vertical-transport field-effect transistor, which is wrapped about the one or more semiconductor fins, are currently formed.

公开(公告)号：US20200279768A1

公开(公告)日：2020-09-03

申请号：US16290178

申请日：2019-03-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Vimal K. Kamineni ,  Ruilong Xie ,  Kangguo Cheng ,  Adra V. Carr

IPC分类号： H01L21/768 ,  H01L23/532

摘要： Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A first field-effect transistor includes a first source/drain region, and a second field-effect transistor includes a second source/drain region. A first contact is arranged over the first source/drain region, and a second contact is arranged over the second source/drain region. A portion of a dielectric layer, which is composed of a low-k dielectric material, is laterally arranged between the first contact and the second contact.

公开(公告)号：US10741668B2

公开(公告)日：2020-08-11

申请号：US15654234

申请日：2017-07-19

申请人： GLOBALFOUNDRIES INC.

发明人： Bala Haran ,  Ruilong Xie ,  Balaji Kannan ,  Katsunori Onishi ,  Vimal K. Kamineni

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

摘要： The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.

公开(公告)号：US10734499B2

公开(公告)日：2020-08-04

申请号：US15986031

申请日：2018-05-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/20 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088

摘要： Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

公开(公告)号：US10727308B2

公开(公告)日：2020-07-28

申请号：US16548335

申请日：2019-08-22

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/45 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

摘要： One device disclosed herein includes a gate above a semiconductor substrate, the gate comprising a gate structure and a gate cap, and conductive source/drain metallization structures adjacent the gate, each of the conductive source/drain metallization structures having a front face and a recess defined in each of the conductive source/drain metallization structures. In this example, the device further includes a spacer structure comprising recess filling portions that substantially fill the recesses and a portion that extends across a portion of the upper surface of the gate cap, wherein a portion of the gate cap is exposed within the spacer structure, an insulating material within the spacer structure and on the exposed portion of the gate cap, a gate contact opening that exposes a portion of an upper surface of the gate structure, and a conductive gate contact structure in the conductive gate contact opening.