Invention Grant
- Patent Title: Memory array with power-efficient read architecture
- Patent Title (中): 具有省电读取架构的内存阵列
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Application No.: US14462078Application Date: 2014-08-18
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Publication No.: US09208891B2Publication Date: 2015-12-08
- Inventor: Toru Tanzawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G11C16/24 ; G11C5/02 ; G11C16/04 ; G11C11/56

Abstract:
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.
Public/Granted literature
- US20140355352A1 MEMORY ARRAY WITH POWER-EFFICIENT READ ARCHITECTURE Public/Granted day:2014-12-04
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