Invention Grant
US09208891B2 Memory array with power-efficient read architecture 有权
具有省电读取架构的内存阵列

Memory array with power-efficient read architecture
Abstract:
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.
Public/Granted literature
Information query
Patent Agency Ranking
0/0