Invention Grant
- Patent Title: Receiver architecture for memory reads
- Patent Title (中): 存储器读取的接收器架构
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Application No.: US14055761Application Date: 2013-10-16
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Publication No.: US09213487B2Publication Date: 2015-12-15
- Inventor: Narasimhan Vasudevan , Li Pan , Michael Thomas Fertsch , Nan Chen
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Novak Druce Connolly Bove + Quigg LLP
- Main IPC: G06F13/00
- IPC: G06F13/00 ; G06F13/12 ; G06F13/38 ; G06F3/06 ; G06F13/16 ; G11C7/10

Abstract:
A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters.
Public/Granted literature
- US20150106538A1 RECEIVER ARCHITECTURE FOR MEMORY READS Public/Granted day:2015-04-16
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