Invention Grant
- Patent Title: Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
- Patent Title (中): 使用正阱偏置电压和负字线电压擦除闪存器件中的存储单元的方法
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Application No.: US13895591Application Date: 2013-05-16
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Publication No.: US09214233B2Publication Date: 2015-12-15
- Inventor: Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
- Applicant: Conversant Intellectual Property Management Inc.
- Applicant Address: CA Ottawa, Ontario
- Assignee: Conversant Intellectual Property Management Inc.
- Current Assignee: Conversant Intellectual Property Management Inc.
- Current Assignee Address: CA Ottawa, Ontario
- Agency: Borden Ladner Gervais LLP
- Agent Shin Hung
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G11C16/02 ; G11C16/08
Abstract:
A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
Public/Granted literature
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