Invention Grant
- Patent Title: Shielded gate trench FET with multiple channels
- Patent Title (中): 多通道屏蔽栅沟槽FET
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Application No.: US13553285Application Date: 2012-07-19
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Publication No.: US09224853B2Publication Date: 2015-12-29
- Inventor: James Pan
- Applicant: James Pan
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/40 ; H01L29/423
Abstract:
In one embodiment, an apparatus can include a trench extending into a semiconductor region of a first conductivity type, an electrode disposed in the trench, and a source region of the first conductivity type abutting a sidewall of the trench. The apparatus can include a first well region of a second conductivity type disposed in the semiconductor region below the source region and abutting the sidewall of the trench lateral to the electrode where the second conductivity type is opposite the first conductivity type. The apparatus can also include a second well region of the second conductivity type disposed in the semiconductor region and abutting the sidewall of the trench, and a third well region of the first conductivity type disposed between the first well region and the second well region.
Public/Granted literature
- US20120280312A1 STRUCTURE AND METHOD FOR FORMING SHIELDED GATE TRENCH FET WITH MULTIPLE CHANNELS Public/Granted day:2012-11-08
Information query
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