Invention Grant
US09229872B2 Semiconductor chip with adaptive BIST cache testing during runtime
有权
半导体芯片在运行时具有自适应BIST缓存测试
- Patent Title: Semiconductor chip with adaptive BIST cache testing during runtime
- Patent Title (中): 半导体芯片在运行时具有自适应BIST缓存测试
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Application No.: US13843639Application Date: 2013-03-15
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Publication No.: US09229872B2Publication Date: 2016-01-05
- Inventor: Christopher Wilkerson , Jawad Nasrullah , Kelvin Kwan
- Applicant: Christopher Wilkerson , Jawad Nasrullah , Kelvin Kwan
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott, LLP
- Main IPC: G06F12/08
- IPC: G06F12/08
Abstract:
A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.
Public/Granted literature
- US20140281254A1 Semiconductor Chip With Adaptive BIST Cache Testing During Runtime Public/Granted day:2014-09-18
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