Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.