Invention Grant
- Patent Title: Layer arrangement and a wafer level package comprising the layer arrangement
- Patent Title (中): 层布置和包括层布置的晶片级封装
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Application No.: US14372015Application Date: 2013-06-18
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Publication No.: US09240362B2Publication Date: 2016-01-19
- Inventor: Vivek Chidambaram , Ling Xie , Ranganathan Nagarajan , Bangtao Chen , Beng Yeung Ho
- Applicant: Agency for Science, Technology and Research
- Applicant Address: SG Singapore
- Assignee: Agency for Science, Technology and Research
- Current Assignee: Agency for Science, Technology and Research
- Current Assignee Address: SG Singapore
- Agency: Winstead, P.C.
- Priority: SG201204609 20120620
- International Application: PCT/SG2013/000252 WO 20130618
- International Announcement: WO2013/191656 WO 20131227
- Main IPC: H01L23/20
- IPC: H01L23/20 ; H01L23/26 ; C22C14/00 ; C22C19/03 ; B81B7/00 ; B81C1/00
Abstract:
The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).
Public/Granted literature
- US20150130039A1 LAYER ARRANGEMENT AND A WAFER LEVEL PACKAGE COMPRISING THE LAYER ARRANGEMENT Public/Granted day:2015-05-14
Information query
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