Invention Grant
US09240454B1 Integrated circuit including a liner silicide with low contact resistance
有权
集成电路包括具有低接触电阻的衬里硅化物
- Patent Title: Integrated circuit including a liner silicide with low contact resistance
- Patent Title (中): 集成电路包括具有低接触电阻的衬里硅化物
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Application No.: US14520781Application Date: 2014-10-22
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Publication No.: US09240454B1Publication Date: 2016-01-19
- Inventor: Qing Liu , Walter Kleemeier
- Applicant: STMicroelectronics, Inc.
- Applicant Address: US TX Coppell
- Assignee: STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/00 ; H01L21/82 ; H01L29/45 ; H01L27/092 ; H01L21/8238 ; H01L29/78 ; H01L29/778
Abstract:
An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.
Information query
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