公开(公告)号：US20160218070A1

公开(公告)日：2016-07-28

申请号：US15090996

申请日：2016-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.

Abstract translation: 各种实施例便于集成电路的管芯保护。 在一个实施例中，多层结构形成在多个层次上并沿着模具的边缘，以防止和检测对模具的损坏。 所述多层结构包括支撑层，覆盖所述支撑层的第一多个介电柱，填充所述第一多个介电柱之间的空间的金属层，覆盖所述第一多个介电柱和所述金属层的绝缘层，第二 覆盖绝缘层的多个介电柱，以及填充第二多个介电柱之间的空间的第二金属层。

公开(公告)号：US08900990B2

公开(公告)日：2014-12-02

申请号：US13731878

申请日：2012-12-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Walter Kleemeier ,  Cindy Goldberg

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract translation: 金属互连通过组合镶嵌工艺和减去金属蚀刻形成在一体中。 在电介质层中形成宽沟槽。 导电材料沉积在宽沟槽中。 在导电材料中蚀刻沟槽以描绘多个金属插塞，每个金属插头接触由宽沟槽暴露的相应金属轨道。

公开(公告)号：US09633909B2

公开(公告)日：2017-04-25

申请号：US14942504

申请日：2015-11-16

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  Qing Liu

IPC: H01L21/38 ,  H01L21/22 ,  H01L21/8238 ,  H01L29/45 ,  H01L27/092 ,  H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

公开(公告)号：US20160300857A1

公开(公告)日：2016-10-13

申请号：US14680392

申请日：2015-04-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L27/12 ,  H01L29/417 ,  H01L27/092 ,  H01L21/324 ,  H01L21/306 ,  H01L29/08 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/66545

Abstract: A junctionless field effect transistor on an insulating layer of a substrate includes a fin made of semiconductor material doped with a dopant of a first conductivity type. A channel made of an epitaxial semiconductor material region doped with a dopant of a second conductivity type is in contact with a top surface of the fin. An insulated metal gate straddles the channel. A source connection is made to the epitaxial semiconductor material region on one side of said insulated metal gate, and a drain connection is made to the epitaxial semiconductor material region on an opposite side of said insulated metal gate. The epitaxial channel may further be grown from and be in contact with opposed side surfaces of the fin.

Abstract translation: 在基板的绝缘层上的无连接场效应晶体管包括由掺杂有第一导电类型的掺杂剂的半导体材料制成的鳍。 由掺杂有第二导电类型的掺杂剂的外延半导体材料区域形成的沟道与鳍片的顶表面接触。 绝缘金属门横跨通道。 源极连接到所述绝缘金属栅极的一侧上的外延半导体材料区域，并且在所述绝缘金属栅极的相对侧上的外延半导体材料区域进行漏极连接。 外延沟道还可以从翅片的相对的侧表面生长并与其接触。

公开(公告)号：US09240454B1

公开(公告)日：2016-01-19

申请号：US14520781

申请日：2014-10-22

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Walter Kleemeier

IPC: H01L27/12 ,  H01L29/00 ,  H01L21/82 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/778

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract translation: 集成电路包括支撑具有源极区和漏极区的晶体管的衬底。 晶体管的源极区和漏极区存在高掺杂浓度的δ掺杂层。 一组触点延伸穿过覆盖晶体管的预金属介电层。 硅化物区域设置在该组触点的底部。 硅化物区域由接触底部存在的金属与晶体管的源极区域和漏极区域上的高掺杂浓度δ-掺杂层之间的水化反应形成。

公开(公告)号：US20140353722A1

公开(公告)日：2014-12-04

申请号：US13907752

申请日：2013-05-31

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Cindy Goldberg ,  Walter Kleemeier

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A graphene capped HEMT device and a method of fabricating same are disclosed. The graphene capped HEMT device includes one or more graphene caps that enhance device performance and/or reliability of an exemplary AlGaN/GaN heterostructure transistor used in high-frequency, high-energy applications, e.g., wireless telecommunications. The HEMT device disclosed makes use of the extraordinary material properties of graphene. One of the graphene caps acts as a heat sink underneath the transistor, while the other graphene cap stabilizes the source, drain, and gate regions of the transistor to prevent cracking during high-power operation. A process flow is disclosed for replacing a three-layer film stack, previously used to prevent cracking, with a one-atom thick layer of graphene, without otherwise degrading device performance. In addition, the HEMT device disclosed includes a hexagonal boron nitride adhesion layer to facilitate deposition of the compound nitride semiconductors onto the graphene.

Abstract translation: 公开了石墨烯封盖HEMT器件及其制造方法。 石墨烯封盖的HEMT器件包括一个或多个石墨烯帽，其增强用于高频，高能量应用（例如无线电信）中的示例性AlGaN / GaN异质结构晶体管的器件性能和/或可靠性。 所公开的HEMT装置利用石墨烯的非凡材料特性。 其中一个石墨烯帽作为晶体管下面的散热器，而另一个石墨烯帽稳定晶体管的源极，漏极和栅极区域，以防止在大功率操作期间的开裂。 公开了一种工艺流程，用于用原子厚的石墨烯层替代先前用于防止裂纹的三层膜堆，而不会使装置性能降低。 此外，所公开的HEMT器件包括六边形氮化硼粘附层，以便于将复合氮化物半导体沉积到石墨烯上。

公开(公告)号：US20140183735A1

公开(公告)日：2014-07-03

申请号：US13731878

申请日：2012-12-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： John H. ZHANG ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng XU ,  Walter Kleemeier ,  Cindy Goldberg

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract translation: 金属互连通过组合镶嵌工艺和减去金属蚀刻形成在一体中。 在电介质层中形成宽沟槽。 导电材料沉积在宽沟槽中。 在导电材料中蚀刻沟槽以描绘多个金属插塞，每个金属插头接触由宽沟槽暴露的相应金属轨道。

公开(公告)号：US20160056249A1

公开(公告)日：2016-02-25

申请号：US14931078

申请日：2015-11-03

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  John Hongguang Zhang

IPC: H01L29/417 ,  H01L29/49 ,  H01L21/84

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

公开(公告)号：US09209305B1

公开(公告)日：2015-12-08

申请号：US14298000

申请日：2014-06-06

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。

公开(公告)号：US20140027933A1

公开(公告)日：2014-01-30

申请号：US14038574

申请日：2013-09-26

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Walter Kleemeier ,  Paul Ferreira ,  Ronald K. Sampson

IPC: H01L23/544 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract translation: 提供了一种装置，其包括具有第一对准结构的第一管芯，所述第一对准结构包括布置成图案的多个第一传输柱和位于所述第一管芯上的第二管芯，所述第二管芯具有第二对准结构，所述第二对准结构包括多个第二 传输列以与第一传输列相同的图案排列。 第一和第二透射柱分别与第一和第二模具的第一表面和第二表面共面。