Invention Grant
- Patent Title: Method of introducing local stress in a semiconductor layer
- Patent Title (中): 在半导体层中引入局部应力的方法
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Application No.: US14451174Application Date: 2014-08-04
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Publication No.: US09240466B2Publication Date: 2016-01-19
- Inventor: Pierre Morin , Denis Rideau , Olivier Nier
- Applicant: STMicroelectronics SA , STMicroelectronics, Inc.
- Applicant Address: FR Montrouge US TX Coppell
- Assignee: STMicroelectronics SA,STMicroelectronics, Inc.
- Current Assignee: STMicroelectronics SA,STMicroelectronics, Inc.
- Current Assignee Address: FR Montrouge US TX Coppell
- Agency: Seed IP Law Group PLLC
- Priority: FR1357807 20130806
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/66 ; H01L21/02 ; H01L21/324 ; H01L21/762 ; H01L29/78 ; H01L27/12

Abstract:
The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
Public/Granted literature
- US20150044826A1 METHOD OF INTRODUCING LOCAL STRESS IN A SEMICONDUCTOR LAYER Public/Granted day:2015-02-12
Information query
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