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公开(公告)号：US09318372B2
公开(公告)日：2016-04-19
申请号：US14526053
申请日：2014-10-28
Inventor： Olivier Nier , Denis Rideau , Pierre Morin , Emmanuel Josse
IPC: H01L21/00 , H01L21/762 , H01L29/78 , H01L27/12 , H01L21/02
CPC classification number: H01L21/76283 , H01L21/02356 , H01L21/02532 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7846 , H01L29/7847 , H01L29/7849
Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。
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公开(公告)号：US09331175B2
公开(公告)日：2016-05-03
申请号：US14452041
申请日：2014-08-05
Applicant: STMicroelectronics SA , STMicroelectronics, Inc.
Inventor： Pierre Morin , Denis Rideau , Olivier Nier
IPC: H01L21/00 , H01L29/66 , H01L21/02 , H01L21/324 , H01L21/762 , H01L29/78 , H01L27/12 , H01L21/84
CPC classification number: H01L29/66772 , H01L21/0217 , H01L21/02532 , H01L21/324 , H01L21/76283 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7843 , H01L29/7847
Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
Abstract translation: 本公开涉及一种应力半导体层的方法，包括：在绝缘体上半导体层（SOI）结构上沉积，该结构具有与绝缘层接触的半导体层，应力层; 通过在所述应力层中形成一个或多个开口来对所述半导体层进行局部应力，所述开口与要形成晶体管沟道的所述半导体层的第一区对齐; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。
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公开(公告)号：US20150118805A1
公开(公告)日：2015-04-30
申请号：US14526081
申请日：2014-10-28
Inventor： Denis Rideau , Elise Baylac , Emmanuel Josse , Pierre Morin , Olivier Nier
IPC: H01L21/8234 , H01L21/324 , H01L29/78 , H01L21/265 , H01L21/84 , H01L21/762
CPC classification number: H01L21/823481 , H01L21/02356 , H01L21/02532 , H01L21/265 , H01L21/26506 , H01L21/3081 , H01L21/3105 , H01L21/31155 , H01L21/324 , H01L21/76224 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7831 , H01L29/7846 , H01L29/7847
Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.
Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠
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公开(公告)号：US20150044826A1
公开(公告)日：2015-02-12
申请号：US14451174
申请日：2014-08-04
Applicant: STMicroelectronics SA , STMicroelectronics, Inc.
Inventor： Pierre Morin , Denis Rideau , Olivier Nier
IPC: H01L29/66 , H01L21/02 , H01L29/78 , H01L21/324 , H01L21/762
CPC classification number: H01L29/66772 , H01L21/0217 , H01L21/324 , H01L21/76283 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7843 , H01L29/7847 , H01L29/785
Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。
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Patent Agency Ranking
公开(公告)号：US09543214B2
公开(公告)日：2017-01-10
申请号：US14526081
申请日：2014-10-28
Inventor： Denis Rideau , Elise Baylac , Emmanuel Josse , Pierre Morin , Olivier Nier
IPC: H01L21/8234 , H01L21/84 , H01L21/762 , H01L29/78 , H01L21/02 , H01L21/265 , H01L21/3115 , H01L21/308 , H01L21/3105 , H01L21/324 , H01L27/12
CPC classification number: H01L21/823481 , H01L21/02356 , H01L21/02532 , H01L21/265 , H01L21/26506 , H01L21/3081 , H01L21/3105 , H01L21/31155 , H01L21/324 , H01L21/76224 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7831 , H01L29/7846 , H01L29/7847
Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.
Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠
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公开(公告)号：US09240466B2
公开(公告)日：2016-01-19
申请号：US14451174
申请日：2014-08-04
Applicant: STMicroelectronics SA , STMicroelectronics, Inc.
Inventor： Pierre Morin , Denis Rideau , Olivier Nier
IPC: H01L21/00 , H01L29/66 , H01L21/02 , H01L21/324 , H01L21/762 , H01L29/78 , H01L27/12
CPC classification number: H01L29/66772 , H01L21/0217 , H01L21/324 , H01L21/76283 , H01L21/84 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7843 , H01L29/7847 , H01L29/785
Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。
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公开(公告)号：US20150118823A1
公开(公告)日：2015-04-30
申请号：US14526053
申请日：2014-10-28
Inventor： Olivier Nier , Denis Rideau , Pierre Morin , Emmanuel Josse
IPC: H01L21/762 , H01L27/12 , H01L21/02 , H01L29/78
CPC classification number: H01L21/76283 , H01L21/02356 , H01L21/02532 , H01L21/76237 , H01L21/823431 , H01L21/845 , H01L27/1203 , H01L29/7846 , H01L29/7847 , H01L29/7849
Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。
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公开(公告)号：US09305828B2
公开(公告)日：2016-04-05
申请号：US14526005
申请日：2014-10-28
Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Denis Rideau , Emmanuel Josse , Olivier Nier
IPC: H01L21/00 , H01L21/762 , H01L21/02 , H01L29/78 , H01L21/84 , H01L21/324
CPC classification number: H01L21/76283 , H01L21/02356 , H01L21/324 , H01L21/76237 , H01L21/84 , H01L21/845 , H01L29/66795 , H01L29/7846 , H01L29/7847
Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.
Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。
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公开(公告)号：US20150118824A1
公开(公告)日：2015-04-30
申请号：US14526005
申请日：2014-10-28
Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Denis Rideau , Emmanuel Josse , Olivier Nier
IPC: H01L21/762 , H01L29/78 , H01L21/02
CPC classification number: H01L21/76283 , H01L21/02356 , H01L21/324 , H01L21/76237 , H01L21/84 , H01L21/845 , H01L29/66795 , H01L29/7846 , H01L29/7847
Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.
Abstract translation: 本发明的一个或多个实施方案涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层和绝缘体层的半导体结构的表面中形成至少两个第一方向的第一沟槽， 要在半导体结构中形成的至少一个第一晶体管的第一尺寸; 执行第一退火以降低绝缘层的粘度; 以及在所述第一退火之后的表面中，在限定所述至少一个晶体管的第二维度的第二方向上形成至少两个第二沟槽。
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