Invention Grant
- Patent Title: Substrate assembly, method of manufacturing substrate assembly and method of manufacturing chip package
- Patent Title (中): 基板组装,基板组装制造方法及芯片封装制造方法
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Application No.: US14209419Application Date: 2014-03-13
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Publication No.: US09245814B2Publication Date: 2016-01-26
- Inventor: Takashi Fushie , Kunihiko Ueno , Hajime Kikuchi
- Applicant: HOYA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: HOYA CORPORATION
- Current Assignee: HOYA CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2013-079773 20130405
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/15 ; G03F7/00 ; H01L23/498 ; H01L21/56

Abstract:
A substrate assembly including a photosensitive etching glass substrate; and a first substrate and a second substrate for interposing both main surfaces of the photosensitive etching glass substrate between them. One of the main surfaces of the photosensitive etching glass substrate is thermally bonded to the first substrate, and the other main surface of the photosensitive etching glass substrate is bonded to the second substrate. When a thermal expansion coefficient of the photosensitive etching glass substrate is defined as C0, and a thermal expansion coefficient of the first substrate is defined as C1, and a thermal expansion coefficient of the second substrate is defined as C2, C1/C2 satisfies a relation of 0.7 or more and 1.3 or less, and at least one of a relation of C0/C1 satisfying less than 0.7 or larger than 1.3, and a relation of C0/C2 satisfying less than 0.7 or larger than 1.3 is satisfied.
Public/Granted literature
- US20140301050A1 SUBSTRATE ASSEMBLY, METHOD OF MANUFACTURING SUBSTRATE ASSEMBLY AND METHOD OF MANUFACTURING CHIP PACKAGE Public/Granted day:2014-10-09
Information query
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