Invention Grant
- Patent Title: Reconfigurable hardware structures for functional pipelining of on-chip special purpose functions
- Patent Title (中): 用于片上专用功能的功能流水线的可重构硬件结构
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Application No.: US13789524Application Date: 2013-03-07
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Publication No.: US09251272B2Publication Date: 2016-02-02
- Inventor: Kathirgamar Aingaran , Garret F. Swart
- Applicant: Oracle International Corporation
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle International Corporation
- Current Assignee: Oracle International Corporation
- Current Assignee Address: US CA Redwood Shores
- Agency: Hickman Palermo Becker Bingham LLP
- Main IPC: G06F17/30
- IPC: G06F17/30 ; G06F9/54 ; G06F9/38 ; G06F12/08 ; G06F12/12 ; G06F15/173 ; G06F12/14 ; G06F21/62 ; H04L29/06 ; G06F15/78

Abstract:
A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory. Consequently, a program that utilizes the method or apparatus, reduces power consumption, consumes less memory bandwidth, and reduces the program's memory footprint.
Public/Granted literature
- US20140095748A1 RECONFIGURABLE HARDWARE STRUCTURES FOR FUNCTIONAL PIPELINING OF ON-CHIP SPECIAL PURPOSE FUNCTIONS Public/Granted day:2014-04-03
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