An exemplary embodiment provides a thin film transistor array panel including: a substrate; a gate line; a semiconductor layer; a data wire layer; a first passivation layer; and a second passivation layer. The gate line is disposed on the substrate and includes a gate electrode. The semiconductor layer is disposed on the substrate. The data wire layer is configured to include a data line disposed on the substrate to cross the gate line, a source electrode connected to the data line, and a drain electrode disposed to face the source electrode. The first passivation layer is disposed on a channel region between the source electrode and the drain electrode. The second passivation layer is disposed on the first passivation layer, the source electrode, and the drain electrode. A width of the first passivation layer disposed on the channel region is equal to or smaller than a distance between the source electrode and the drain electrode.