公开(公告)号：US11675231B2

公开(公告)日：2023-06-13

申请号：US16688882

申请日：2019-11-19

Applicant: Samsung Display Co., Ltd. ,  DONGWOO FINE-CHEM CO., LTD.

Inventor： Baek Hee Lee ,  Donghee Lee ,  Sun-Young Hong ,  Juho Kim ,  Hyungjoo Kim ,  Jongsoo Lee

IPC: G02F1/1335 ,  C08L33/08 ,  C08K5/37 ,  C08K5/372 ,  G02F1/13357 ,  B82Y20/00

CPC classification number: G02F1/133621 ,  C08K5/372 ,  C08L33/08 ,  B82Y20/00 ,  G02F1/133614 ,  G02F2202/023 ,  G02F2202/36

Abstract: A composition for a light conversion layer includes: a base resin; quantum dots; and a thiol compound including at least one thiol group in a molecule.

公开(公告)号：US09397127B2

公开(公告)日：2016-07-19

申请号：US14994975

申请日：2016-01-13

Applicant: Samsung Display Co., Ltd.

Inventor： Sun-Young Hong

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L27/1288 ,  H01L21/467 ,  H01L23/3171 ,  H01L23/3178 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An exemplary embodiment provides a thin film transistor array panel including: a substrate; a gate line; a semiconductor layer; a data wire layer; a first passivation layer; and a second passivation layer. The gate line is disposed on the substrate and includes a gate electrode. The semiconductor layer is disposed on the substrate. The data wire layer is configured to include a data line disposed on the substrate to cross the gate line, a source electrode connected to the data line, and a drain electrode disposed to face the source electrode. The first passivation layer is disposed on a channel region between the source electrode and the drain electrode. The second passivation layer is disposed on the first passivation layer, the source electrode, and the drain electrode. A width of the first passivation layer disposed on the channel region is equal to or smaller than a distance between the source electrode and the drain electrode.

公开(公告)号：US09252160B2

公开(公告)日：2016-02-02

申请号：US14265774

申请日：2014-04-30

Applicant: Samsung Display Co., Ltd.

Inventor： Sun-Young Hong

IPC: H01L29/66 ,  H01L21/00 ,  H01L27/12 ,  H01L29/786 ,  H01L21/467 ,  H01L23/31 ,  H01L29/49

CPC classification number: H01L27/1288 ,  H01L21/467 ,  H01L23/3171 ,  H01L23/3178 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An exemplary embodiment provides a thin film transistor array panel including: a substrate; a gate line; a semiconductor layer; a data wire layer; a first passivation layer; and a second passivation layer. The gate line is disposed on the substrate and includes a gate electrode. The semiconductor layer is disposed on the substrate. The data wire layer is configured to include a data line disposed on the substrate to cross the gate line, a source electrode connected to the data line, and a drain electrode disposed to face the source electrode. The first passivation layer is disposed on a channel region between the source electrode and the drain electrode. The second passivation layer is disposed on the first passivation layer, the source electrode, and the drain electrode. A width of the first passivation layer disposed on the channel region is equal to or smaller than a distance between the source electrode and the drain electrode.

Abstract translation: 一个示例性实施例提供一种薄膜晶体管阵列面板，包括：基板; 一条门线 半导体层; 数据线层; 第一钝化层; 和第二钝化层。 栅极线设置在基板上并且包括栅电极。 半导体层设置在基板上。 数据线层被配置为包括布置在基板上的数据线以跨越栅极线，连接到数据线的源极和设置成面对源电极的漏电极。 第一钝化层设置在源电极和漏极之间的沟道区上。 第二钝化层设置在第一钝化层，源电极和漏电极上。 设置在沟道区上的第一钝化层的宽度等于或小于源电极和漏电极之间的距离。

公开(公告)号：US10852581B2

公开(公告)日：2020-12-01

申请号：US16537743

申请日：2019-08-12

Applicant: Samsung Display Co., Ltd.

Inventor： Dong Hee Lee ,  Baek Hee Lee ,  Sun-Young Hong

IPC: G02F1/13357 ,  F21V8/00

Abstract: A light unit according to an exemplary embodiment includes a light source and an optical member transmitting and converting light emitted from the light source, where the optical member includes a light guide, a low refractive index layer disposed on the light guide and having a smaller refractive index than that of the light guide, and a wavelength conversion layer disposed on the low refractive index layer and including quantum dots, and the low refractive index layer includes a metal.

公开(公告)号：US09443881B2

公开(公告)日：2016-09-13

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jean-Ho Song ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L29/04 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。

公开(公告)号：US20150053984A1

公开(公告)日：2015-02-26

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JEAN-HO SONG ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。