3-D integration using multi stage vias

Invention Grant

US09263324B2 3-D integration using multi stage vias 有权

Title translation: 使用多级通孔的3-D集成

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Patent Title: 3-D integration using multi stage vias
Patent Title (中): 使用多级通孔的3-D集成
Application No.: US14080562

Application Date: 2013-11-14
Publication No.: US09263324B2

Publication Date: 2016-02-16
Inventor: Mukta G. Farooq , Troy L. Graves-Abe
Applicant: GLOBALFOUNDRIES Inc.
Applicant Address: KY Grand Cayman
Assignee: GLOBALFOUNDRIES Inc.
Current Assignee: GLOBALFOUNDRIES Inc.
Current Assignee Address: KY Grand Cayman
Agency: Heslin Rothenberg Farley & Mesiti P.C.
Main IPC: H01L21/4763
IPC: H01L21/4763 ; H01L21/768 ; H01L23/48

Abstract:

A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.

Abstract(Chinese):

可以形成TSV，其具有通过顶部衬底表面形成的顶部截面，以及通过底部衬底表面形成的底部截面。顶部截面可以具有对应于设计规则的最小横截面，并且顶部截面深度可对应于可工作的纵横比。顶部通孔可以被填充或插入，以便可以继续顶部处理。底部通孔可以具有更大的横截面，以便于形成穿过其中的导电路径。底部部分通孔从顶部部分通孔的背面延伸到底部，并且在基板变薄之后形成。可以通过在从接合的顶部和底部部分通孔去除牺牲填充材料之后形成导电路径来完成TSV。

Public/Granted literature

US20140073134A1 3-D INTEGRATION USING MULTI STAGE VIAS Public/Granted day:2014-03-13

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）