公开(公告)号：US10296698B2

公开(公告)日：2019-05-21

申请号：US15378122

申请日：2016-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Troy L. Graves-Abe

IPC: G06F17/50 ,  H01L21/768

Abstract: Various embodiments include approaches for designing through-silicon vias (TSVs) in integrated circuits (ICs). In some cases, a method includes: identifying types of through-silicon vias (TSVs) for placement within an integrated circuit (IC) design based upon an electrical requirement for the TSVs, wherein the IC design includes distinct types of TSVs; calculating etch and fill rates for the IC design with the distinct types of TSVs with common etching and filling processes; and providing fabrication instructions to form the distinct types of TSVs according to the calculated etch and fill rates in the common processes.

公开(公告)号：US09640514B1

公开(公告)日：2017-05-02

申请号：US15084004

申请日：2016-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Lin ,  Troy L. Graves-Abe ,  Donald F. Canaperi ,  Spyridon Skordas ,  Matthew T. Shoudy ,  Binglin Miao ,  Raghuveer R. Patlolla ,  Sanjay C. Mehta

IPC: H01L25/065 ,  H01L21/762 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76251 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/29084 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/83031 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83896 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01008 ,  H01L2924/01014 ,  H01L2924/0503 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/20109 ,  H01L2924/206 ,  H01L2924/2064

Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.

公开(公告)号：US09263324B2

公开(公告)日：2016-02-16

申请号：US14080562

申请日：2013-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  Troy L. Graves-Abe

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.

Abstract translation: 可以形成TSV，其具有通过顶部衬底表面形成的顶部截面，以及通过底部衬底表面形成的底部截面。 顶部截面可以具有对应于设计规则的最小横截面，并且顶部截面深度可对应于可工作的纵横比。 顶部通孔可以被填充或插入，以便可以继续顶部处理。 底部通孔可以具有更大的横截面，以便于形成穿过其中的导电路径。 底部部分通孔从顶部部分通孔的背面延伸到底部，并且在基板变薄之后形成。 可以通过在从接合的顶部和底部部分通孔去除牺牲填充材料之后形成导电路径来完成TSV。

公开(公告)号：US20180165402A1

公开(公告)日：2018-06-14

申请号：US15378122

申请日：2016-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Troy L. Graves-Abe

IPC: G06F17/50 ,  H01L21/768

CPC classification number: G06F17/5077 ,  H01L21/76898

Abstract: Various embodiments include approaches for designing through-silicon vias (TSVs) in integrated circuits (ICs). In some cases, a method includes: identifying types of through-silicon vias (TSVs) for placement within an integrated circuit (IC) design based upon an electrical requirement for the TSVs, wherein the IC design includes distinct types of TSVs; calculating etch and fill rates for the IC design with the distinct types of TSVs with common etching and filling processes; and providing fabrication instructions to form the distinct types of TSVs according to the calculated etch and fill rates in the common processes.

公开(公告)号：US09252133B2

公开(公告)日：2016-02-02

申请号：US14487439

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christopher N. Collins ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Joyce C. Liu ,  Gerd Pfeiffer ,  Thuy L. Tran-Quinn

IPC: H01L23/00 ,  H01L25/065 ,  H01L29/32 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/5384 ,  H01L29/32 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).

Abstract translation: 已经证明用于3D应用的TSV（通过衬底通孔）的形成缺陷取决于所采用的起始半导体衬底的类型。 除了通过博世处理初始形成TSV之外，背面3D晶片处理也显示了对衬底类型的缺陷依赖性。 可以通过利用以1e4 / cc（每立方厘米颗粒）和1e7 / cc之间的密度并且具有小于55nm（纳米）的当量直径的体积微观缺陷（BMD）来实现高产率的TSV形成。

公开(公告)号：US09476927B2

公开(公告)日：2016-10-25

申请号：US14161309

申请日：2014-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Troy L. Graves-Abe ,  Chandrasekharan Kothandaraman ,  Conal E. Murray

IPC: G01R31/02 ,  H01L21/66 ,  H01L23/48 ,  G01R31/26 ,  G01M5/00

CPC classification number: G01R31/021 ,  G01M5/0033 ,  G01M5/0083 ,  G01R31/26 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure to detect changes in the integrity of vertical electrical connection structures including a semiconductor layer and an electrically conductive material extending through an entire depth of the semiconductor layer. The electrically conductive material has a geometry that encloses a pedestal portion of the semiconductor layer within an interior perimeter of the electrically conductive material. At least one semiconductor device is present on the pedestal portion of the semiconductor layer within the perimeter of the electrically conductive material.

Abstract translation: 检测包括半导体层和延伸穿过半导体层的整个深度的导电材料的垂直电连接结构的完整性变化的结构。 导电材料具有在导电材料的内部周边内包围半导体层的基座部分的几何形状。 至少一个半导体器件存在于导电材料的周边内的半导体层的基座部分上。

公开(公告)号：US09257336B2

公开(公告)日：2016-02-09

申请号：US14522633

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Troy L. Graves-Abe

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  Y10T29/41 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/014

Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.