Invention Grant
US09263327B2 Minimizing void formation in semiconductor vias and trenches 有权
最小化半导体通孔和沟槽中的空隙形成

Minimizing void formation in semiconductor vias and trenches
Abstract:
Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.
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