Invention Grant
- Patent Title: Minimizing void formation in semiconductor vias and trenches
- Patent Title (中): 最小化半导体通孔和沟槽中的空隙形成
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Application No.: US14310314Application Date: 2014-06-20
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Publication No.: US09263327B2Publication Date: 2016-02-16
- Inventor: Xunyuan Zhang , Sean X. Lin
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY
- Agency: Heslin, Rothenberg, Farley & Mesiti
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/288

Abstract:
Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.
Public/Granted literature
- US20150371899A1 MINIMIZING VOID FORMATION IN SEMICONDUCTOR VIAS AND TRENCHES Public/Granted day:2015-12-24
Information query
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