Invention Grant
- Patent Title: Methods of forming transistors
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Application No.: US14836257Application Date: 2015-08-26
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Publication No.: US09263341B2Publication Date: 2016-02-16
- Inventor: Deepak Chandra Pandey , Haitao Liu , Fawad Ahmed , Kamal M. Karda
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/8234 ; H01L21/306

Abstract:
Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
Public/Granted literature
- US20150364377A1 Methods of Forming Transistors Public/Granted day:2015-12-17
Information query
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