Invention Grant
US09264039B2 Circuit and method for on-die termination, and semiconductor memory device including the same
有权
用于片上端接的电路和方法，以及包括其的半导体存储器件
- Patent Title: Circuit and method for on-die termination, and semiconductor memory device including the same
- Patent Title (中): 用于片上端接的电路和方法，以及包括其的半导体存储器件
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Application No.: US14202323Application Date: 2014-03-10
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Publication No.: US09264039B2Publication Date: 2016-02-16
- Inventor: Ho-Seok Seol , Seung-Jun Bae , Young-Soo Sohn , Ho-Sung Song
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee & Morse, P.C.
- Priority: KR10-2013-0026947 20130313
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K19/003 ; H03K19/00
Abstract:
An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.
Public/Granted literature
- US20140266299A1 CIRCUIT AND METHOD FOR ON-DIE TERMINATION, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Public/Granted day:2014-09-18
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